An Architecture to Enable Lifetime Testing in CMPs

As CMOS technology scaling continues to low nanometers, aging and device wear-out related degradation is a looming concern. With device wear-out mechanisms such as NBTI and PBTI, catalyzed by higher temperature, transistor performance worsens with time. Similarly with electromigration, interconnects become increasingly resistive until they become non-functional. Such phenomena initially manifest as delay defects, which in the due course of time turn into permanent defects. Online testing is needed to avert situations in which such defects show up as errors during operation. In this paper we propose an architecture that can assist online testing at various levels in a Chip Multiprocessor (CMP). The proposed solution revolves around the incorporation of a small and simple, functionally limited core called the Sentry Core (SC) in the CMP. This core is responsible for assisting with testing of the functional cores in a CMP. Since SC is small, it is assumed to be hardened during design and remain fault-free during useful lifetime of the chip. We explore two of the many possible online testing schemes possible with this architecture. In the first scheme, we explore the use of SC in triggering opportunistic DMR to verify functional correctness of the cores. In the second scheme, we evaluate the effectiveness of the SC in monitoring and potentially detecting errors in operation of the cache coherence protocol. Results indicate that even though incorporation of the SC results in an area overhead in the CMP, the rich functionality it provides with respect to testing and fault tolerance justifies this cost.